1. Field of the Invention
The present invention relates to a power device and a method for manufacturing the same.
2. Description of the Related Art
Double-diffused metal oxide semiconductor (DMOS) transistors, which are MOS-type transistors driven by voltage and which may bear high current, have begun attracting greater attention. DMOS transistors integrated with bipolar-type integrated circuits may be classified as lateral DMOS (LDMOS) transistors, or vertical DMOS (VDMOS) transistors, depending on the direction of current flowing therein. In particular, for DMOS transistors operating at a high voltage, it is advantageous that the DMOS transistors be VDMOS transistors because VDMOS transistors occupy smaller area on a substrate than LDMOS transistors. Among VDMOS transistors, N-channel VDMOS transistors, which have sound electrical characteristics, are typically used in bipolar-type integrated circuits.
N-channel VDMOS transistors are connected to N+ buried layers, using the N+ buried layers as drains. The drains may be heavily doped with impurity ions, thus isolation layers with considerable surface areas are required in order to isolate VDMOS transistors from each other. In a case where doping concentration is increased and drive-in time (e.g., time necessary to drive dopant atoms deeper into a semiconductor wafer of the device) long, a large-sized semiconductor device with a wider isolation layer may be required in order to reduce a drain-source on-resistance (Rdson), so as to maintain breakdown voltage of the semiconductor device. Where high-dose ion implantation is used for reducing Rdson, a thermal process requiring a sufficient amount of heat may be needed to diffuse impurity ions into a lower portion of the semiconductor device.
Due to the increased heat required, the area of the semiconductor device may increase in a horizontal direction during the diffusion. Additionally where high-energy ion implantation is used to reduce Rdson, since high-dose doping may be difficult, high-energy ion implantation techniques may be limited when reducing Rdson, since these techniques cannot avoid the diffusion of impurity ions in a vertical direction. Thus, high-energy ion implantation techniques may be disadvantageous to the scaling of the semiconductor device. As a result, a trade-off may exist between a desire to reduce Rdson, and a desire to reduce an area of an isolation layer.
However, the need for mounting small-sized, highly-integrated semiconductor devices that consume a small amount of power on a semiconductor chip continues to increase. Thus, a technique for achieving appropriate performance from semiconductor devices by reducing Rdson and scaling down the semiconductor devices along horizontal and vertical dimensions is desired.